xilinx - Does aborting a partial FPGA reconfiguration possibly result in an undefined state? -

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i'm working on reconfiguration controller reconfigurable cpu. 1 of features tried implement handle crc errors properly, , allow aborts during reconfiguration. using virtex7 board , described in ug702.pdf (page 98) reloading bitstream after crc error isn't problem, abort can performed shown in ug470_7series_config.pdf (page 48).

at first glance seems work described in documentation, on crc error reconfiguration controller notifies cpu , cpu gives controller fresh bitstream. also, cpu can send controller abort command , controller abort described in docs.

hovewer, seems work sporadically, whole system freezes, nonsensical exceptions, , unconditional jumps not taken seems.

i not sure whether messed somewhere or expected, since containers partial bitstreams go interconnected pipeline , bus. remember have read in xilinx pdf bitstream not configured until desynch command @ end of bitstream encountered. mean fabric not affected until full partial bitstream loaded onto fabric, without errors, , therefore couldn't affect rest of design. or partially loaded partial bitstream configured onto fpga , can trigger sorts of weird signals on output ?


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