vhdl - dual port RAM write data -

i little bit confused dual port ram,my target write , read data.i want write data.like on address 128 , on rest adresses 0.is works correctly,because im not sure case statements useful? how write correctly data in ram? reading this article , think need true dual port ram.i have next code.

library ieee; use ieee.std_logic_1164.all; entity true_dual_port_ram_single_clock  generic (   data_width : natural := 8;   addr_width : natural := 6  );  port (   clk : in std_logic;     addr_a : in natural range 0 2**addr_width - 1;   addr_b : in natural range 0 2**addr_width - 1;   data_a : in std_logic_vector((data_width-1) downto 0);   data_b : in std_logic_vector((data_width-1) downto 0);   we_a : in std_logic := '1';   we_b : in std_logic := '1';   q_a : out std_logic_vector((data_width -1) downto 0);   q_b : out std_logic_vector((data_width -1) downto 0)  ); end true_dual_port_ram_single_clock; architecture rtl of true_dual_port_ram_single_clock  -- build 2-d array type ram  subtype word_t std_logic_vector((data_width-1) downto 0);  type memory_t array((2**addr_width - 1) downto 0) of word_t;  -- declare ram signal.  shared variable ram : memory_t;   begin  process(clk)  begin  if(rising_edge(clk)) -- port   if(we_a = '1')       ram(addr_a) := data_a;     -- read-during-write on same port returns new data             case addr_a             when 0 =>                   q_a <= "10000000";             when 16 =>                   q_a <= "10000000";             when others =>                   q_a <="00000000";         end case;    q_a <= data_a;   else    -- read-during-write on mixed port returns old data             case addr_a             when 0 =>                   q_a <= "10000000";             when 16 =>                   q_a <= "10000000";             when others =>                   q_a <="00000000";         end case;    q_a <= ram(addr_a);   end if;  end if;  end process;  process(clk)  begin  if(rising_edge(clk)) -- port b   if(we_b = '1')             case addr_a             when 0 =>                   q_b <= "10000000";             when 16 =>                   q_b <= "10000000";             when others =>                   q_b <="00000000";         end case;    ram(addr_b) := data_b;    -- read-during-write on same port returns new data    q_b <= data_b;   else    -- read-during-write on mixed port returns old data            if(we_b = '1')             case addr_b             when 0 =>                   q_b <= "10000000";             when 16 =>                   q_b <= "10000000";             when others =>                   q_b <="00000000";         end case;    q_b <= ram(addr_b);   end if;  end if;   end if;  end process; end rtl;